M. Morris Mano,
M. Morris R. Mano,
Michael Ciletti,
Michael D. Ciletti
e.a.
Pearson Education
e druk, 2018
9781292231167
Digital Design, Global Edition
Specificaties
Paperback, blz.
|
Engels
Pearson Education |
2018
ISBN13: 9781292231167
Rubricering
Levertijd ongeveer 9 werkdagen
Gratis verzonden
Samenvatting
For introductory courses on digital design in an Electrical Engineering, Computer Engineering, or Computer Science department.
A clear and accessible approach to teaching the basic tools, concepts, and applications of digital design.
A modern update to a classic, authoritative text, Digital Design, 6th Edition teaches the fundamental concepts of digital design in a clear, accessible manner. The text presents the basic tools for the design of digital circuits and provides procedures suitable for a variety of digital applications. Like the previous editions, this edition of Digital Design supports a multimodal approach to learning, with a focus on digital design, regardless of language. Recognizing that three public-domain languages–Verilog, VHDL, and SystemVerilog–all play a role in design flows for today’s digital devices, the 6th Edition offers parallel tracks of presentation of multiple languages, but allows concentration on a single, chosen language.
Specificaties
Inhoudsopgave
<p>Preface </p> <p>1 Digital Systems and Binary Numbers </p> <p>1.1 Digital Systems </p> <p>1.2 Binary Numbers </p> <p>1.3 Number-Base Conversions </p> <p>1.4 Octal and Hexadecimal Numbers </p> <p>1.5 Complements of Numbers </p> <p>1.6 Signed Binary Numbers </p> <p>1.7 Binary Codes </p> <p>1.8 Binary Storage and Registers </p> <p>1.9 Binary Logic </p> <p> </p> <p>2 Boolean Algebra and Logic Gates </p> <p>2.1 Introduction </p> <p>2.2 Basic Definitions </p> <p>2.3 Axiomatic Definition of Boolean Algebra </p> <p>2.4 Basic Theorems and Properties of Boolean Algebra </p> <p>2.5 Boolean Functions </p> <p>2.6 Canonical and Standard Forms </p> <p>2.7 Other Logic Operations </p> <p>2.8 Digital Logic Gates </p> <p>2.9 Integrated Circuits </p> <p> </p> <p>3 Gate-Level Minimization </p> <p>3.1 Introduction </p> <p>3.2 The Map Method </p> <p>3.3 Four-Variable K-Map </p> <p>3.4 Product-of-Sums Simplification </p> <p>3.5 Don’t-Care Conditions </p> <p>3.6 NAND and NOR Implementation </p> <p>3.7 Other Two-Level Implementations </p> <p>3.8 Exclusive-OR Function </p> <p>3.9 Hardware Description Languages (HDLs) </p> <p> </p> <p>4 Combinational Logic </p> <p>4.1 Introduction </p> <p>4.2 Combinational Circuits </p> <p>4.3 Analysis of Combinational Circuits </p> <p>4.4 Design Procedure </p> <p>4.5 Binary Adder—Subtractor </p> <p>4.6 Decimal Adder </p> <p>4.7 Binary Multiplier </p> <p>4.8 Magnitude Comparator </p> <p>4.9 Decoders </p> <p>4.10 Encoders </p> <p>4.11 Multiplexers </p> <p>4.12 HDL Models of Combinational Circuits </p> <p> </p> <p>5 Synchronous Sequential Logic </p> <p>5.1 Introduction </p> <p>5.2 Sequential Circuits </p> <p>5.3 Storage Elements: Latches </p> <p>5.4 Storage Elements: Flip-Flops </p> <p>5.5 Analysis of Clocked Sequential Circuits </p> <p>5.6 Synthesizable HDL Models of Sequential Circuits </p> <p>5.7 State Reduction and Assignment </p> <p>5.8 Design Procedure </p> <p> </p> <p>6 Registers and Counters </p> <p>6.1 Registers </p> <p>6.2 Shift Registers </p> <p>6.3 Ripple Counters </p> <p>6.4 Synchronous Counters </p> <p>6.5 Other Counters </p> <p>6.6 HDL Models of Registers and Counters </p> <p> </p> <p>7 Memory and Programmable Logic </p> <p>7.1 Introduction </p> <p>7.2 Random-Access Memory </p> <p>7.3 Memory Decoding </p> <p>7.4 Error Detection and Correction </p> <p>7.5 Read-Only Memory </p> <p>7.6 Programmable Logic Array </p> <p>7.7 Programmable Array Logic </p> <p>7.8 Sequential Programmable Devices </p> <p> </p> <p>8 Design at the Register Transfer Level </p> <p>8.1 Introduction </p> <p>8.2 Register Transfer Level (RTL) Notation </p> <p>8.3 RTL descriptions VERILOG (Edge- and Level-Sensitive Behaviors) </p> <p>8.4 Algorithmic State Machines (ASMs) </p> <p>8.5 Design Example (ASMD Chart) </p> <p>8.6 HDL Description of Design Example </p> <p>8.7 Sequential Binary Multiplier </p> <p>8.8 Control Logic </p> <p>8.9 HDL Description of Binary Multiplier </p> <p>8.10 Design with Multiplexers </p> <p>8.11 Race-Free Design (Software Race Conditions) </p> <p>8.12 Latch-Free Design (Why Waste Silicon?) </p> <p>8.13 System Verilog–An Introduction </p> <p> </p> <p>9 Laboratory Experiments with Standard ICs and FPGAs </p> <p>9.1 Introduction t</p>